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74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
Rev. 03 -- 8 May 2009 Product data sheet
1. General description
The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device. The 74HC3G14; 74HCT3G14 provides three inverting buffers with Schmitt trigger inputs which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
2. Features
I I I I I I I Wide supply voltage range from 2.0 V to 6.0 V High noise immunity Low power dissipation Balanced propagation delays Unlimited input rise and fall times Multiple package options ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from -40 C to +85 C and -40 C to +125 C
3. Applications
I Wave and pulse shaper for highly noisy environments I Astable multivibrators I Monostable multivibrators
4. Ordering information
Table 1. Ordering information Package Temperature range Name 74HC3G14DP 74HCT3G14DP 74HC3G14DC 74HCT3G14DC 74HC3G14GD 74HCT3G14GD -40 C to +125 C XSON8U -40 C to +125 C VSSOP8 -40 C to +125 C TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number
plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
5. Marking
Table 2. Marking Marking code H14 T14 H14 T14 H14 T14 Type number 74HC3G14DP 74HCT3G14DP 74HC3G14DC 74HCT3G14DC 74HC3G14GD 74HCT3G14GD
6. Functional diagram
1A
1Y
3Y
3A
2A
2Y
A
001aah729
Y
mna025
001aah728
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one Schmitt trigger)
7. Pinning information
7.1 Pinning
74HC3G14 74HCT3G14
1A 1 2 3 4 8 7 6 5 VCC 1Y 3A 2Y
74HC3G14 74HCT3G14
1A 3Y 2A GND 1 2 3 4
001aak035
3Y 8 7 6 5 VCC 1Y 3A 2Y 2A GND
001aak036
Transparent top view
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT996-2 (XSON8U)
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
2 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
7.2 Pin description
Table 3. Symbol 1A, 2A, 3A GND 1Y, 2Y, 3Y VCC Pin description Pin 1, 3, 6 4 7, 5, 2 8 Description data input ground (0 V) data output supply voltage
8. Functional description
Table 4. Input nA L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table[1] Output nY H L
9. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot
[1] [2]
Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V VO = -0.5 V to VCC + 0.5 V
[1] [1] [1] [1] [1]
Min -0.5 -50 -65
[2]
Max +7.0 20 20 25 +50 +150 300
Unit V mA mA mA mA mA C mW
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8U package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
3 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
10. Recommended operating conditions
Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC VI VO Tamb supply voltage input voltage output voltage ambient temperature Conditions Min 2.0 0 0 -40 74HC3G14 Typ 5.0 +25 Max 6.0 VCC VCC +125 Min 4.5 0 0 -40 74HCT3G14 Typ 5.0 +25 Max 5.5 VCC VCC +125 V V V C Unit
11. Static characteristics
Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C. Symbol Parameter 74HC3G14 VOH HIGH-level VI = VT+ or VT- output voltage IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level VI = VT+ or VT- output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current VI = VCC or GND; VCC = 6.0 V 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.32 5.81 0 0 0 0.15 0.16 2.0 0.1 0.1 0.1 0.26 0.26 0.1 1.0 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1.0 10 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 20 V V V V V V V V V V A A pF Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
supply current per input pin; VCC = 6.0 V; VI = VCC or GND; IO = 0 A; input capacitance HIGH-level VI = VT+ or VT- output voltage IO = -20 A; VCC = 4.5 V IO = -4.0 mA; VCC = 4.5 V LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V input leakage current VI = VCC or GND; VCC = 5.5 V
74HCT3G14 VOH 4.4 4.18 4.5 4.32 0 0.15 0.1 0.26 0.1 4.4 4.13 0.1 0.33 1.0 4.4 3.7 0.1 0.4 1.0 V V V V A
VOL
II
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
4 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
Table 7. Static characteristics ...continued Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 C. Symbol Parameter ICC ICC Conditions Min supply current per input pin; VCC = 5.5 V; VI = VCC or GND; IO = 0 A; additional per input; supply current VCC = 4.5 V to 5.5 V; VI = VCC - 2.1 V; IO = 0 A input capacitance 25 C Typ Max 1.0 300 -40 C to +85 C -40 C to +125 C Unit Min Max 10 375 Min Max 20 410 A A
CI
-
2.0
-
-
-
-
-
pF
Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions Min 74HC3G14 VT+ positive-going threshold voltage see Figure 6, Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VT- negative-going threshold voltage see Figure 6, Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VH hysteresis voltage (VT+ - VT-); see Figure 6, Figure 7 and Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 74HCT3G14 VT+ positive-going threshold voltage see Figure 6, Figure 7 VCC = 4.5 V VCC = 5.5 V VT- negative-going threshold voltage see Figure 6, Figure 7 VCC = 4.5 V VCC = 5.5 V VH hysteresis voltage (VT+ - VT-); see Figure 6, Figure 7 and Figure 8 VCC = 4.5 V VCC = 5.5 V 0.40 0.40 0.71 0.67 0.40 0.40 V V 0.50 0.60 0.87 1.11 1.20 1.40 0.50 0.60 1.20 1.40 1.20 1.40 V V 1.20 1.40 1.58 1.78 1.90 2.10 1.20 1.40 1.90 2.10 1.90 2.10 V V 0.30 0.60 0.80 0.60 1.13 1.40 1.00 1.40 1.70 0.30 0.60 0.80 1.00 1.40 1.70 1.00 1.40 1.70 V V V 0.30 1.13 1.50 0.60 1.47 2.06 0.90 2.00 2.60 0.30 1.13 1.50 0.90 2.00 2.60 0.90 2.00 2.60 V V V 1.00 2.30 3.00 1.18 2.60 3.46 1.50 3.15 4.20 1.00 2.30 3.00 1.50 3.15 4.20 1.50 3.15 4.20 V V V 25 C Typ Max -40 C to +125 C Min Max (85 C) Max (125 C) Unit
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
5 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
11.1 Waveforms transfer characteristics
VO VT+ VI VT- VH
VH VT- VT+
VI
mna207
VO
mna208
Fig 6.
Transfer characteristic
Fig 7.
Definition of VT+, VT- and VH
2.0 ICC (mA)
mna031
3.0 ICC (mA)
mna032
2.0
1.0
1.0
0 0 2.5 VI (V) 5.0
0 0 3.0 VI (V) 6.0
a. VCC = 4.5 V. Fig 8. Typical 74HCT3G14 transfer characteristics
b. VCC = 5.5 V.
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
6 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
100 ICC (A)
mna028
1.0 ICC (mA) 0.8
mna029
0.6 50 0.4
0.2
0 0 1.0 VI (V) 2.0
0 0 2.5 VI (V) 5.0
a. VCC = 2.0 V
1.6 ICC (mA)
b. VCC = 4.5 V
mna030
0.8
0 0 3.0 VI (V) 6.0
c. Fig 9.
VCC = 6.0 V Typical 74HC3G14 transfer characteristics
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
7 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
12. Dynamic characteristics
Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions Min 74HC3G14 tpd propagation delay nA to nY; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time nY; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD power dissipation capacitance propagation delay transition time power dissipation capacitance
tpd is the same as tPLH and tPHL tt is the same as tTLH and tTHL CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of the outputs.
[2] [1]
25 C Typ Max
-40 C to +125 C Min Max (85 C) Max (125 C)
Unit
[3]
53 16 13 20 7 5 10
125 25 21 75 15 13 -
-
155 31 26 95 19 16 -
190 38 32 110 22 19 -
ns ns ns ns ns ns pF
VI = GND to VCC
-
74HCT3G14 tpd tt CPD nA to nY; see Figure 10 VCC = 4.5 V nY; see Figure 10 VCC = 4.5 V VI = GND to VCC - 1.5 V
[3] [2] [1]
-
21 6 10
32 15 -
-
40 19 -
48 22 -
ns ns pF
[1] [2] [3]
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
8 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
13. Waveforms
VI nA input GND t PHL VOH nY output VOL t THL VM VM
10 %
VM
VM
t PLH
90 %
t TLH
mna722
Measurement points are given in Table 10. VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. The data input (nA) to output (nY) propagation delays and output transition times Table 10. Type 74HC3G14 74HCT3G14 Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
9 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VCC
VCC
G
VI
VO
RL
S1
DUT
RT CL
open
001aad983
Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.
Fig 11. Test circuit for measuring switching times Table 11. Type 74HC3G14 74HCT3G14 Test data Input VI GND to VCC GND to 3.0 V tr, tf 6 ns 6 ns Load CL 50 pF 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
10 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
14. Application information
The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: Padd = fi x (tr x ICC(AV) + tf x ICC(AV)) x VCC where: Padd = additional power dissipation (W); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ICC(AV) = average additional supply current (A). ICC(AV) differs with positive or negative input transitions, as shown in Figure 12 and Figure 13. An example of a relaxation circuit using the 74HC3G14/74HCT3G14 is shown in Figure 14.
200 ICC(AV) (A) 150
mna036
positive-going edge 100
50
negative-going edge 0 0 2.0 4.0 VCC (V) 6.0
linear change of VI between 0.1VCC to 0.9VCC.
Fig 12. ICC(AV) as a function of VCC for 74HC3G14
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
11 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
200 ICC(AV) (A) 150
mna058
positive-going edge
100
50
negative-going edge
0 0 2 4 VCC (V) 6
linear change of VI between 0.1VCC to 0.9VCC.
Fig 13. ICC(AV) as a function of VCC for 74HCT3G14
R
C
mna035
For 74HC3G14: f = -- --------------------For 74HCT3G14: f = -- ------------------------
1 T
1 0.8 x RC
1 T
1 0.67 x RC
Fig 14. Relaxation oscillator
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
12 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
15. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
Fig 15. Package outline SOT505-2 (TSSOP8)
74HC_HCT3G14_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
13 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 16. Package outline SOT765-1 (VSSOP8)
74HC_HCT3G14_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
14 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm
SOT996-2
D
B
A
E
A
A1
detail X terminal 1 index area e1 L1
1
e
b
4
v w
M M
CAB C
C y1 C y
L2
L
8 5
X
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1
OUTLINE VERSION SOT996-2
REFERENCES IEC --JEDEC JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 07-12-18 07-12-21
Fig 17. Package outline SOT996-2 (XSON8U)
74HC_HCT3G14_3 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
15 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
16. Abbreviations
Table 12. Acronym CMOS DUT ESD HBM MM Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model
17. Revision history
Table 13. Revision history Release date 20090508 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT3G14_2 Document ID 74HC_HCT3G14_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC3G14GD and 74HCT3G14GD (XSON8U package) Product specification Product specification 74HC_HCT3G14_1 -
74HC_HCT3G14_2 74HC_HCT3G14_1
20031104 20020723
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
16 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
74HC_HCT3G14_3
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 -- 8 May 2009
17 of 18
NXP Semiconductors
74HC3G14; 74HCT3G14
Triple inverting Schmitt trigger
20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Waveforms transfer characteristics. . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 May 2009 Document identifier: 74HC_HCT3G14_3

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